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VECTORALAB EDGE

Specs, Integration & Roadmap

Complete technical specs, software integration stack and development timeline

Machine Context

Supported Machine Types

VectoraLab Edge is designed for any rotating machinery that generates vibration. The DSP pipeline and TinyML model are optimized for the fault frequency ranges of the following machine categories.

Electric Motors
AC induction, BLDC, servo motors — 0.5 kW to 500 kW.
Primary use case
Centrifugal Pumps
Single-stage, multi-stage, submersible and inline pumps.
Gearboxes
Spur, helical, planetary and worm gear configurations.
Rolling Bearings
Ball, roller, tapered and thrust bearings — BPFO/BPFI detection.
High sensitivity
Fans & Blowers
Centrifugal fans, axial fans, industrial blowers.
Compressors
Reciprocating, screw, centrifugal compressors.

Integration

Integration Stack

VectoraLab Edge integrates across the full industrial software and hardware stack — from bare-metal firmware to cloud analytics platforms.

Firmware / RTOS
FreeRTOSSTM32CubeIDEHAL / LL driversCMSIS-DSPX-CUBE-AI
Communication
UARTSPICANModbus RTUMQTT (host-side)
Host Platform
VectoraLab PlatformRaspberry PiIndustrial PCPLC Gateway
Cloud / Analytics
InfluxDBGrafanaAWS IoTAzure IoT HubCustom REST API
Development Tools
STM32CubeIDETFLite MicroPython SDKJupyter Notebooks

Specifications

Complete Technical Specifications

CategorySpecificationValueNote
MCUPart NumberSTM32H750VBT6LQFP100
MCUCoreARM Cortex-M7With FPU
MCUClock~480 MHzPLL
MCUSRAM864 KBMulti-bank
MCUFlash128 KB + ext. QSPI16 MB QSPI
SensorPart NumberIIS3DWBSTMicroelectronics
SensorType3-Axis AccelerometerMEMS
SensorOutput Data Rate26.7 kHzFixed
SensorBandwidthDC – 6 kHzFlat response
SensorNoise Density75 µg/√HzTypical
SensorFull Scale±2 to ±16 gConfigurable
DSPFrame Size2048 samplesPer axis
DSPOverlap50 %1024 advance
DSPFFT Size2048-point real FFTCMSIS-DSP
DSPFeatures32 per frameFloat32
TinyMLModel1D-CNN3-class
TinyMLQuantizationINT8PTQ
TinyMLLatency< 12 msPer frame
TinyMLModel Size< 32 KBFlash
Health ScoreRange0 – 100Continuous
Health ScoreGood Zone≥ 80Configurable
Health ScoreDegrading Zone50 – 79Configurable
Health ScoreCritical Zone< 50Configurable
CommsInterfaceUART / SPI / CANSelectable
CommsBaud Rate921600 bpsUART default
PowerActive~85 mWFull pipeline
PowerSleep< 15 mWSTOP2

Status

Implementation Status

Current development status of all major hardware subsystems and software components.

  • DoneSTM32H750 BSP & HAL configuration
  • DoneIIS3DWB SPI DMA acquisition
  • DoneCircular double-buffer framing
  • DoneHanning window + 2048-pt FFT (CMSIS)
  • DoneTime-domain feature extraction (5×3)
  • DoneSpectral sub-band energy (8 bands)
  • DoneX-CUBE-AI INT8 1D-CNN deployment
  • DoneHealth Score output (0–100)
  • DoneUART burst transmission
  • In ProgressCAN bus output driverTesting
  • In ProgressPython host-side SDKBeta
  • In ProgressFreeRTOS multi-task optimizationv0.9
  • PlannedHardware PCB v1 (4-layer)
  • PlannedISO 10816 compliance validation
  • PlannedModbus RTU gateway

Roadmap

Development Roadmap

Planned milestones for the VectoraLab Edge hardware platform through 2025.

Q1 2025
Core Firmware
  • STM32H750 BSP
  • IIS3DWB DMA driver
  • CMSIS-DSP pipeline
  • INT8 inference
Q2 2025
Integration & SDK
  • Python host SDK
  • UART/CAN drivers
  • FreeRTOS tasks
  • Platform connector
Q3 2025
Hardware PCB
  • 4-layer PCB design
  • EMC filtering
  • IP67 enclosure
  • Prototype run
Q4 2025
Validation & Launch
  • Field trials
  • ISO 10816 validation
  • CE marking
  • Production release

Engineering Transparency

Engineering Transparency

VectoraLab Edge is built on open standards and fully documented signal processing principles. There are no black-box algorithms — every computation is traceable and reproducible.

Open DSP Algorithms
All DSP operations use CMSIS-DSP — an open-source library from Arm. FFT, windowing, and statistical routines are fully documented.
Documented Feature Set
Each of the 32 features has a mathematical definition, expected range, and known fault sensitivity documented in the Engineering Reference.
Auditable Inference
The TinyML model architecture, training dataset provenance, and quantization methodology are disclosed in the Model Card.
Configurable Thresholds
Health Score zone thresholds are user-configurable via UART commands — not hardcoded. Operators can tune to their specific machinery.

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Specs, Integration & Roadmap | VectoraLab Edge